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A Fast Linearization Method to Evaluate The Effects of Circuits Contingencies Upon System Load-Bus Voltages

1982; Institute of Electrical and Electronics Engineers; Volume: PAS-101; Issue: 10 Linguagem: Inglês

10.1109/tpas.1982.317044

ISSN

0018-9510

Autores

K. T. Khu, M. G. Lauby, David Bowen,

Tópico(s)

Silicon Carbide Semiconductor Technologies

Resumo

A fast linearization method devised to evaluate the effects of single or multiple-circuit contingencies upon the system load-bus voltages is presented.

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