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An 8.0-Gb/s HyperTransport Transceiver for 32-nm SOI-CMOS Server Processors

2012; Institute of Electrical and Electronics Engineers; Volume: 47; Issue: 11 Linguagem: Inglês

10.1109/jssc.2012.2211697

1558-173X

Alvin L. S. Loke, Bruce A. Doyle, Sanjeev K. Maheshwari, Dennis Fischette, Charles L. Wang, Tin Tin Wee, Emerson S. Fang,

Electromagnetic Compatibility and Noise Suppression

We present an 8.0-Gb/s HyperTransport source-synchronous I/O integrated in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design capping at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels by incorporating several jitter- and power-reduction enhancements. First, a high-bandwidth digital clean-up PLL is introduced to attenuate high-frequency jitter in the received forwarded clock before the data is sampled. This PLL achieves a highly programmable jitter bandwidth of 20-296 MHz (measured with 0.2 UI pp input jitter) and 0.90-1.50 ps output rms jitter by implementing an extended bang-bang phase detector for additional phase-error magnitude information and flexible bang-bang control of a current-starved ring-based oscillator. Second, several power-hungry circuits, namely the transmitter input FIFO and output driver as well as the receiver deserializer, are redesigned for 8.0-Gb/s operation to maintain thermal compatibility with the existing 45-nm socket package. The fabricated 20-lane I/O consumes 1.70 W at 8.0 Gb/s with an energy efficiency of 11.8 pJ/bit. This reflects a 4.9% increase in HyperTransport power consumption and only 0.3% increase in total processor target power relative to 45-nm operation at 6.4 Gb/s.