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A 64-bit carry look ahead adder using pass transistor BiCMOS gates

1996; Institute of Electrical and Electronics Engineers; Volume: 31; Issue: 6 Linguagem: Inglês

10.1109/4.509867

1558-173X

K. Ueda, Hajime Suzuki, K. Suda, Hirofumi Shinohara, K. Mashiko,

Analog and Mixed-Signal Circuit Design

This paper describes a 64-bit two-stage carry look ahead adder utilizing pass transistor BiCMOS gate. The new pass transistor BiCMOS gate has a smaller intrinsic delay time than conventional BiCMOS gates. Furthermore, this gate has a rail-to-rail output voltage. Therefore the next gate does not have a large degradation of its driving capability. The exclusive OR and NOR gate using the pass transistor BiCMOS gate shows a speed advantage over CMOS gates under a wide variance in load capacitance. The pass transistor BiCMOS gates were applied to full adders, carry path circuits, and carry select circuits. In consequence, a 64-bit two-stage carry look ahead adder was fabricated using a 0.5 /spl mu/m BiCMOS process with single polysilicon and double-metal interconnections. A critical path delay time of 3.5 ns was observed at a supply voltage of 3.3 V. This is 25% better than the result of the adder circuit using CMOS technology. Even at the supply voltage of 2.0 V, this adder is faster than the CMOS adder.