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A TCP offload accelerator for 10 Gb/s ethernet in 90-nm CMOS

2003; Institute of Electrical and Electronics Engineers; Volume: 38; Issue: 11 Linguagem: Inglês

10.1109/jssc.2003.818294

1558-173X

Yatin Hoskote, B. Bloechel, G. Dermer, Vasantha Erraguntla, D. Finan, Jason Howard, D. Klowden, S. Narendra, Greg Ruhl, James Tschanz, Sriram Vangal, V. Veeramachaneni, H. Wilson, Jianzhong Xu, Nitin Borkar,

Radio Frequency Integrated Circuit Design

This programmable engine is designed to offload TCP inbound processing at wire speed for 10-Gb/s Ethernet, supporting 64-byte minimum packet size. This prototype chip employs a high-speed core and a specialized instruction set. It includes hardware support for dynamically reordering out-of-order packets. In a 90-nm CMOS process, the 8-mm 2 experimental chip has 460 K transistors. First silicon has been validated to be fully functional and achieves 9.64-Gb/s packet processing performance at 1.72 V and consumes 6.39 W.