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A self-aligned elevated source/drain MOSFET

1990; Institute of Electrical and Electronics Engineers; Volume: 11; Issue: 9 Linguagem: Inglês

10.1109/55.62957

1558-0563

J.R. Pfiester, R.D. Sivan, H.M. Liaw, C.A. Seelbach, C.D. Gunderson,

Integrated Circuits and Semiconductor Failure Analysis

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior. >