A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module
2012; Institute of Physics; Volume: 7; Issue: 03 Linguagem: Inglês
10.1088/1748-0221/7/03/c03008
ISSN1748-0221
AutoresM. Büchele, H. Fischer, M. Gorzellik, F. Herrmann, K. Königsmann, C. Schill, S. Schopferer,
Tópico(s)Photonic and Optical Devices
ResumoThe GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine cards. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In contrast to common TDC concepts, the input signal is sampled by 16 equidistant phase-shifted clocks. A particular challenge of the design is the minimum skew routing of the input signals to the sampling flip-flops. We present measurement results for the differential nonlinearity and the time resolution of the TDC readout system.
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