Evolution of materials technology for stacked-capacitors in 65nm embedded-DRAM
2005; Elsevier BV; Volume: 49; Issue: 11 Linguagem: Inglês
10.1016/j.sse.2005.10.024
ISSN1879-2405
AutoresE. Gerritsen, N. Emonet, C. Caillat, Nicolas Jourdan, Marc Piazza, D. Fraboulet, B. Boeck, A. Berthelot, S. E. Smith, P. Mazoyer,
Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoThe architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes.
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