Portal de Periódicos da CAPES

A 100 ns 5 V only 64Kx1 MOS dynamic RAM

1980; Institute of Electrical and Electronics Engineers; Volume: 15; Issue: 5 Linguagem: Inglês

10.1109/jssc.1980.1051480

1558-173X

Jay Chan, J.J. Barnes, C.Y. Wang, J.M. De Blasi, Michelle Guidry,

Advancements in Semiconductor Devices and Circuit Design

A new high performance 36500 mil/SUP 2/ 64K dynamic RAM has been designed and incorporates: 1) a twisted-metal bit-line architecture, 2) an ultrasensitive sense amplifier with self-restore to V/SUB DD/, 3) internal constant-voltage supply to memory cell plate, 4) a bit-line equalizer and full-size reference capacitor, 5) high-performance enhancement-depletion mode inverter-buffer circuits, 6) TTL negative undershoot protection on address circuits, and 7) active hold-down transistors for both X and Y drivers. A nominal 100 ns access time and power dissipation of less than 150 mW was observed during active operation with a 20 mW power dissipation in the standby mode.