Packaging design concept simulator for electronic circuit
2000; Wiley; Volume: 31; Issue: 1 Linguagem: Romeno
10.1002/(sici)1520-684x(200001)31
ISSN1520-684X
Autores Tópico(s)Manufacturing Process and Optimization
ResumoSystems and Computers in JapanVolume 31, Issue 1 p. 59-69 Packaging design concept simulator for electronic circuit Toosaku Kojima, Toosaku Kojima Production Engineering Research Lab., Hitachi, Ltd., Yokohama, Japan 244-0817Search for more papers by this authorTazu Nomoto, Tazu Nomoto Production Engineering Research Lab., Hitachi, Ltd., Yokohama, Japan 244-0817Search for more papers by this author Toosaku Kojima, Toosaku Kojima Production Engineering Research Lab., Hitachi, Ltd., Yokohama, Japan 244-0817Search for more papers by this authorTazu Nomoto, Tazu Nomoto Production Engineering Research Lab., Hitachi, Ltd., Yokohama, Japan 244-0817Search for more papers by this author First published: 22 December 1999 https://doi.org/10.1002/(SICI)1520-684X(200001)31:1 3.0.CO;2-8AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinkedInRedditWechat Abstract When designing a printed circuit board, details of the composition of packaging such as the numbers of layers and channels could not be easily determined; therefore, when the design process proceeded to designing a package, trial-and-error processes were often repeated because of the indefinite numbers of layers and channels. Consequently, the design period can be effectively shortened by quantitatively estimating the configuration of the package when a circuit is designed, because it can prevent the problem that after a circuit is designed, the wiring cannot be accommodated in a package and the circuit must be redesigned. The authors established a technology for estimating and evaluating the difficulty of a package depending on a channel requirement ratio. In addition, the authors increased the accuracy of estimation by referring to a database that stores the details of successful packages, indexed according to the configuration. However, several types of package configurations must be selected. Therefore, an index of the number of disabled channels has been introduced as a disturbance factor to wiring patterns, and the wiring detour ratio and an aspect ratio of board were also taken into account, so that a total length of wiring can be estimated precisely, and an optimum package configuration can be selected with a minimum total length of wiring. Therefore, the authors are convinced that the period for developing a printed circuit board can be shortened, using the technique developed by them. © 1999 Scripta Technica, Syst Comp Jpn, 31(1): 59-69, 2000 REFERENCES 1 Matsui N. Optimum design of high-density printed circuit boards. JICR Japan 1989; J72-C-II: 660–667. Google Scholar 2 Seraphim DP. Chip-module-package interfaces. IEEE Trans CHMT, CHMT-1 1978: 305–309. Web of Science®Google Scholar 3 Wakabayashi Y et al. A study on accommodation of wires in high-density printed circuit board. JICE Japan, 1974;CPM-74. Google Scholar 4 Kojima T et al. Methods of estimating assembly of circuit boards. '94 Spring General Meeting, ICE Japan, D-232. Google Scholar 5 Kojima T et al. Automatic estimation system for assembly of printed circuit boards. '95 Spring General Meeting, ICE Japan, D-215. Google Scholar 6 Kojima T et al. Automatic estimation methods for assembly of printed circuit boards. JICE Japan 1989;J79-D-II: 1301–1304. Google Scholar 7 Kojima T et al. Automatic estimation methods for ease of packaging printed circuit board. JICE Japan 1989;J79-D-II: 1305–1307. Google Scholar 8 Kojima T. Estimation system for package configuration in circuit design. '96 General Meeting, ICE Japan, D-146. Google Scholar 9 Kojima T. Estimation system for total wiring length in circuit design. JICE Japan, System Society Meeting, D-125, 1996. Google Scholar 10 Donath W. Placement and average interconnection length of computer logic. IEEE Trans CAS-264, 1979. Google Scholar 11 Kojima T. Package concept simulator for electronic circuit. '97 Spring General Meeting, ICE Japan, D-8-8. Google Scholar 12 Nakayama S. Floor runners for designing printed circuit boards coming onstage. Nikkei Electronics, No. 663, p 97–105, 1996. Google Scholar Volume31, Issue1January 2000Pages 59-69 ReferencesRelatedInformation
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