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Ge0.97Sn0.03 p-channel metal-oxide-semiconductor field-effect transistors: Impact of Si surface passivation layer thickness and post metal annealing

2013; American Institute of Physics; Volume: 114; Issue: 4 Linguagem: Inglês

10.1063/1.4816695

1520-8850

Pengfei Guo, Genquan Han, Xiao Gong, Bin Liu, Yue Yang, Wei Wang, Qian Zhou, Jisheng Pan, Zheng Zhang, Eng Soon Tok, Yee‐Chia Yeo,

Nanowire Synthesis and Applications

A low-temperature (∼370 °C) Si2H6 treatment was used to form an ultrathin Si layer on a Ge0.97Sn0.03 channel layer on Ge substrate in the fabrication of Ge0.97Sn0.03 channel pMOSFETs. The impact of the Si passivation layer thickness on the electrical characteristics of Ge0.97Sn0.03 pMOSFETs was investigated. By increasing the thickness of Si passivation layer from 4 to 7 monolayers (ML), the effective hole mobility μeff at an inversion carrier density Ninv of 1 × 1013 cm−2 was improved by ∼19% ± 4%. This is attributed to reduced carrier scattering by charges found at the interface between the Si layer and the gate dielectric. In addition, the effects of post metal annealing (PMA) were investigated. It was observed that the mid-gap interface trap density Dit was reduced in devices with PMA. Ge0.97Sn0.03 pMOSFETs with PMA have improved intrinsic transconductance Gm,int, subthreshold swing S, and μeff as compared to the control devices without PMA.