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Exploiting Thread-Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline

2008; Electronics and Telecommunications Research Institute; Volume: 30; Issue: 4 Linguagem: Inglês

10.4218/etrij.08.0107.0343

2233-7326

Jae‐Geun Oh, Seok Joong Hwang, Huong Giang Nguyen, Areum Kim, Seon Wook Kim, Chulwoo Kim, Jong‐Kook Kim,

Embedded Systems Design Techniques

ETRI JournalVolume 30, Issue 4 p. 576-586 Regular PaperFree Access Exploiting Thread-Level Parallelism in Lockstep Execution by Partially Duplicating a Single Pipeline Jaegeun Oh, Jaegeun OhSearch for more papers by this authorSeok Joong Hwang, Seok Joong HwangSearch for more papers by this authorHuong Giang Nguyen, Huong Giang NguyenSearch for more papers by this authorAreum Kim, Areum KimSearch for more papers by this authorSeon Wook Kim, Seon Wook KimSearch for more papers by this authorChulwoo Kim, Chulwoo KimSearch for more papers by this authorJong-Kook Kim, Jong-Kook KimSearch for more papers by this author Jaegeun Oh, Jaegeun OhSearch for more papers by this authorSeok Joong Hwang, Seok Joong HwangSearch for more papers by this authorHuong Giang Nguyen, Huong Giang NguyenSearch for more papers by this authorAreum Kim, Areum KimSearch for more papers by this authorSeon Wook Kim, Seon Wook KimSearch for more papers by this authorChulwoo Kim, Chulwoo KimSearch for more papers by this authorJong-Kook Kim, Jong-Kook KimSearch for more papers by this author First published: 01 August 2008 https://doi.org/10.4218/etrij.08.0107.0343Citations: 2 Jaegeun Oh (phone: 82 2 3290 3892, email: [email protected]), Seok Joong Hwang (email: [email protected]), Huong Giang Nguyen (email: [email protected]), Areum Kim (email: [email protected]), Seon Wook Kim (phone: + 82 2 3290 3251, email: [email protected]), Chulwoo Kim (email: [email protected]), and Jong-Kook Kim (email: [email protected]) are with the School of Electrical Engineering, Korea University, Seoul, Rep. of Korea AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Abstract In most parallel loops of embedded applications, every iteration executes the exact same sequence of instructions while manipulating different data. This fact motivates a new compiler-hardware orchestrated execution framework in which all parallel threads share one fetch unit and one decode unit but have their own execution, memory, and write-back units. This resource sharing enables parallel threads to execute in lockstep with minimal hardware extension and compiler support. Our proposed architecture, called multithreaded lockstep execution processor (MLEP), is a compromise between the single-instruction multiple-data (SIMD) and symmetric multithreading/chip multiprocessor (SMT/CMP) solutions. The proposed approach is more favorable than a typical SIMD execution in terms of degree of parallelism, range of applicability, and code generation, and can save more power and chip area than the SMT/CMP approach without significant performance degradation. For the architecture verification, we extend a commercial 32-bit embedded core AE32000C and synthesize it on Xilinx FPGA. Compared to the original architecture, our approach is 13.5% faster with a 2-way MLEP and 33.7% faster with a 4-way MLEP in EEMBC benchmarks which are automatically parallelized by the Intel compiler. References 1H.C. Hunter and J.H. Moreno, "A New Look at Exploiting Data Parallelism in Embedded Systems," CASE, 2003, pp. 159– 169. 2I. Karkowski and H. Corporaal, "Exploiting Fine- and Coarse-Grain Parallelism in Embedded Programs," PACT, 1998, pp. 60– 67. 3J.E. Smith and G.S. Sohi, "The Microarchitecture of Superscalar Processors," Proc. of the IEEE, Vol. 83, Dec. 1995, pp. 1609– 1624. 4D.M. Tullsen et al., "Simultaneous Multithreading: Maximizing On-Chip Parallelism," ISCA-22, June 1995. 5 Analog Devices, Inc. ADSP-BF561 Blackfin Embedded Symmetric Multiprocessor Rev. 0. 6ARM. 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Citing Literature Volume30, Issue4August 2008Pages 576-586 ReferencesRelatedInformation