Percolation path and dielectric-breakdown-induced-epitaxy evolution during ultrathin gate dielectric breakdown transient
2003; American Institute of Physics; Volume: 83; Issue: 11 Linguagem: Inglês
10.1063/1.1611649
ISSN1520-8842
AutoresChih Hang Tung, K. L. Pey, Lei Tang, M. Radhakrishnan, Wen H. Lin, Félix Palumbo, S. Lombardo,
Tópico(s)Integrated Circuits and Semiconductor Failure Analysis
ResumoA physical model has been developed which complies with the experimental observation on the failure mechanism of ultrathin gate oxide breakdown during constant voltage stress. Dynamic equilibrium needs to be established between the percolation conductive path and the dielectric breakdown induced epitaxy (DBIE) formation during gate dielectric breakdown transient. The model is capable of linking the percolation model, soft breakdown, and hard breakdown to the DBIE growth for a variety of stress conditions and gate oxide thickness without involving new empirical parameters.
Referência(s)