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GaAs low-power integrated circuits for a high-speed digital signal processor

1989; Institute of Electrical and Electronics Engineers; Volume: 36; Issue: 2 Linguagem: Inglês

10.1109/16.19922

1557-9646

H.P. Singh, R.A. Sadler, J.A. Irvine, G.E. Gorder,

Low-power high-performance VLSI design

A high-speed 4-bit ALU, 4*4-bit multiplier, and 8*8-bit multiplier/accumulator have been implemented in low-power GaAs enhanced/depletion E/D direct-coupled FET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate MESFET process. The 4-bit ALU performs at up to 1.2 GHz with only 131-mW power dissipation. The multiplication time for the 4*4-bit array multiplier is 940 ps, which is the fastest multiplication time reported for any semiconductor technology. The 8*8-bit two's complement multiplier/accumulator uses 4278 FETs (1317 logic gates) and exhibits a multiplication time of 3.17 ns. the fastest yet reported for a multiplier of this type. Yield on the best wafer for the 4*4-bit and 8*8-bit circuits is 94 and 43%, respectively. A digital arithmetic subsystem has been demonstrated, consisting of the 8*8-bit multiplier/accumulator, two of the 4-bit ALUs, three logical multiplexers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 MHz. >