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An overview of today’s high-level synthesis tools

2012; Springer Science+Business Media; Volume: 16; Issue: 3 Linguagem: Inglês

10.1007/s10617-012-9096-8

1572-8080

Wim Meeus, Kristof Van Beeck, Toon Goedemé, Jan Meel, Dirk Stroobandt,

VLSI and Analog Circuit Testing

High-level synthesis (HLS) is an increasingly popular approach in electronic design automation (EDA) that raises the abstraction level for designing digital circuits. With the increasing complexity of embedded systems, these tools are particularly relevant in embedded systems design. In this paper, we present our evaluation of a broad selection of recent HLS tools in terms of capabilities, usability and quality of results. Even though HLS tools are still lacking some maturity, they are constantly improving and the industry is now starting to adopt them into their design flows.