Schottky-Barrier S/D MOSFETs With High-<tex>$Kappa$</tex>Gate Dielectrics and Metal-Gate Electrode
2004; Institute of Electrical and Electronics Engineers; Volume: 25; Issue: 5 Linguagem: Inglês
10.1109/led.2004.826569
ISSN1558-0563
AutoresShiyang Zhu, H.Y. Yu, S. J. Whang, J.H. Chen, Chen Shen, Chunxiang Zhu, S.J. Lee, M.F. Li, D.S.H. Chan, Won Jong Yoo, Anyan Du, C. H. Tung, Jagar Singh, Albert Chin, Dim‐Lee Kwong,
Tópico(s)Integrated Circuits and Semiconductor Failure Analysis
ResumoThis letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-/spl kappa/ gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi sourece/drain (S/D) , excellent electrical performance of I/sub on//I/sub off//spl sim/10/sup 7/-10/sup 8/ and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi/sub 2-x/ S/D , I/sub on//I/sub off/ can reach /spl sim/10/sup 5/ at V/sub ds/ of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-/spl kappa/ dielectric and metal-gate materials to be used in the future generation CMOS technology.
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