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Prefetch unit for vector operations on scalar computers

1992; ACM SIGARCH; Volume: 20; Issue: 4 Linguagem: Inglês

10.1145/142880.142891

1943-5851

Ivan Sklenář,

Interconnection Networks and Systems

Current caches are not adequate for vector operations. A new kind of support for vector operations, called prefetch unit, is designed to improve the performance of the scalar (SISD) processors. The prefetch unit can be used for any SISD architecture and also for many kinds of MIMD architectures. It may run in parallel and asynchronously with other parts of processor. It keeps trace of the history of memory references, and therefore initializes rarely any superfluous prefetches.