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A fast lock digital phase-locked-loop architecture for wireless applications

2003; Institute of Electrical and Electronics Engineers; Volume: 39; Issue: 2 Linguagem: Inglês

10.1109/tcsii.2003.809711

1558-125X

Amr Fahim, M.I. Elmasry,

Analog and Mixed-Signal Circuit Design

A fast lock digital phase-locked-loop (PLL) frequency synthesizer for wireless applications is reported. The main advantages of the architecture include small area and digitally selectable frequency resolution. Also, a fully digital solution to reducing the phase lock time is introduced. This work is also supported by a nonlinear analytical analysis of the locking mechanism for PLLs.