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A new NMOS temperature-stable voltage reference

1978; Institute of Electrical and Electronics Engineers; Volume: 13; Issue: 6 Linguagem: Inglês

10.1109/jssc.1978.1052048

1558-173X

R. Blauschild, P.A. Tucci, R.S. Muller, Ralf Meyer,

Low-power high-performance VLSI design

An NMOS voltage reference has been developed that exhibits extremely low drift with temperature. The reference is based on the difference between the gate/source voltages of enhancement and depletion-mode NMOS transistors. The theoretical dependence of the reference voltage on both device and circuit parameters is analyzed and conditions for optimal performance are derived. The reference NMOS transistors are biased to the optimizing current levels by a unique feedback circuit. The measured output voltage drift in the integrated realization agrees well with theory and is less than 5 parts per million per degree Celsius over the temperature range -55/spl deg/ to +125/spl deg/C.