Portal de Periódicos da CAPES

Realization of Gmicro/200

1988; Institute of Electrical and Electronics Engineers; Volume: 8; Issue: 2 Linguagem: Inglês

10.1109/40.526

1937-4143

H. Inayoshi, I. Kawasaki, T. Nishimukai, Ken Sakamura,

Distributed and Parallel Computing Systems

The Gmicro/200, a microprocessor that has been developed as part of Japan's TRON (The Real-Time Operating Nucleus) project, is described. This microprogram-based processor with six-state pipeline, 730000 transistors and on-chip caches will serve in an engineering workstation or a high-speed graphics accelerator system. The authors discuss features of the instruction set; memory management; handling of exceptions, interrupts and traps; and the implementation of the Gmicro/200. >