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A space-efficient flash translation layer for CompactFlash systems

2002; Institute of Electrical and Electronics Engineers; Volume: 48; Issue: 2 Linguagem: Inglês

10.1109/tce.2002.1010143

1558-4127

Jesung Kim, Jong‐Min Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho,

Parallel Computing and Optimization Techniques

Flash memory is becoming increasingly important as nonvolatile storage for mobile consumer electronics due to its low power consumption and shock resistance. However, it imposes technical challenges in that a write should be preceded by an erase operation, and that this erase operation can be performed only in a unit much larger than the write unit. To address these technical hurdles, an intermediate software layer called a flash translation layer (FTL) is generally employed to redirect logical addresses from the host system to physical addresses in flash memory. Previous approaches have performed this address translation at the granularity of either a write unit (page) or an erase unit (block). We propose a novel FTL design that combines the two different granularities in address translation. This is motivated by the idea that coarse grain address translation lowers the resources required to maintain translation information, which is crucial in mobile consumer products for cost and power consumption reasons, while fine grain address translation is efficient in handling small size writes. Performance evaluation based on trace-driven simulation shows that the proposed scheme significantly outperforms previously proposed approaches.