A 1.8-V 700-mb/s/pin 512-mb DDR-II SDRAM with on-die termination and off-chip driver calibration
2004; Institute of Electrical and Electronics Engineers; Volume: 39; Issue: 6 Linguagem: Inglês
10.1109/jssc.2004.827806
ISSN1558-173X
AutoresChangsik Yoo, Kye-Hyun Kyung, Kyu-Nam Lim, Hi-Choon Lee, J.-W. Chai, Nak-Won Heo, Dong‐Jin Lee, Chang‐Hyun Kim,
Tópico(s)Advancements in PLL and VCO Technologies
ResumoA 512-Mb DDR-II SDRAM has achieved 700-Mb/s/pin operation at 1.8-V supply voltage with 0.12-/spl mu/m DRAM process. The low supply voltage presents challenges in high data rate and signal integrity. Circuit techniques such as hierarchical I/O lines, local sense amplifier, and fully shielded data lines without area penalty have provided improved data access time and, thus, high data rate can be achieved. Off-chip driver with calibrated strength and on-die termination are utilized to give sufficient signal integrity for over 533-Mb/s/pin operation.
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