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An 18-μA standby current 1.8-V, 200-MHz microprocessor with self-substrate-biased data-retention mode

1999; Institute of Electrical and Electronics Engineers; Volume: 34; Issue: 11 Linguagem: Inglês

10.1109/4.799853

1558-173X

Hiroyuki Mizuno, K. Ishibashi, T. Shimura, Toshihiro Hattori, Susumu Narita, Kenji Shiozawa, Shuji Ikeda, K. Uchiyama,

Advancements in Semiconductor Devices and Circuit Design

A low-standby-current 1.8-V, 200-MHz microprocessor has been fabricated with a 0.2-/spl mu/m, five-metal, dual-oxide-thickness, CMOS technology and two power down modes (i.e., a standby mode and a data-retention mode). The microprocessor uses a switched substrate-impedance scheme to bias substrates in the standby mode while maintaining a 200-MHz operating speed. Data-retention capability during the standby mode is also maintained. This mode achieves 46.5-/spl mu/A standby current. The microprocessor also offers a battery-backup capability in a self-substrate-biased data-retention mode. This makes it possible to apply a deep substrate bias without increasing the gate-induced drain leakage current or p-n junction current. The current consumption is only 17.8 /spl mu/A when operating off a 1-V supply in the data-retention mode.