Dual-$k$ Spacer Device Architecture for the Improvement of Performance of Silicon n-Channel Tunnel FETs
2010; Institute of Electrical and Electronics Engineers; Volume: 57; Issue: 10 Linguagem: Inglês
10.1109/ted.2010.2057195
ISSN1557-9646
AutoresH. G. Virani, R. Adari, Anil Kottantharayil,
Tópico(s)Ferroelectric and Negative Capacitance Devices
ResumoA dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more so for the underlap structures. Performance improvements are illustrated and explained for SiO 2 , Al 2 O 3 , and HfO 2 gate dielectrics. The structure is optimized for the on-state current without degrading the off-state current or the subthreshold slope.
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