Portal de Periódicos da CAPES

Simulating spin systems on IANUS, an FPGA-based computer

2007; Elsevier BV; Volume: 178; Issue: 3 Linguagem: Inglês

10.1016/j.cpc.2007.09.006

1879-2944

Francesco Belletti, M. Cotallo, A. Cruz, L. A. Fernández, A. Gordillo-Guerrero, A. Maiorano, Filippo Mantovani, Enzo Marinari, V. Martı́n-Mayor, A. Muñoz Sudupe, D. Navarro, S. Pérez-Gaviro, J. J. Ruiz-Lorenzo, Sebastiano Fabio Schifano, D. Sciretti, A. Tarancón, R. Tripiccione, J. L. Velasco,

Advanced Data Storage Technologies

We describe the hardwired implementation of algorithms for Monte Carlo simulations of a large class of spin models. We have implemented these algorithms as VHDL codes and we have mapped them onto a dedicated processor based on a large FPGA device. The measured performance on one such processor is comparable to O(100) carefully programmed high-end PCs: it turns out to be even better for some selected spin models. We describe here codes that we are currently executing on the IANUS massively parallel FPGA-based system.