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3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

2010; Institute of Electrical and Electronics Engineers; Volume: 45; Issue: 4 Linguagem: Inglês

10.1109/jssc.2010.2040310

1558-173X

Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda,

Electrical and Thermal Properties of Materials

This paper describes a three-dimensional (3-D) system integration of a full-fledged processor chip and two memory chips using inductive coupling. To attain a 3-D communication link with a smaller area and lower power-consumption, shortening the link distance and preventing signal degradation due to unused inductors are important challenges. Therefore, we developed a new 3D-integrated wire-penetrated multi-layer structure for a shorter link distance and an open-skipped-inductor scheme for suppressing signal degradation. In addition, to avoid undefined-value propagation in stacking multi-memories using an inductive-coupling link, we proposed a memory-access-control scheme with a pinpoint-data-capture scheme. We demonstrate that three fabricated chips can be successfully AC-coupled using inductive coupling. The power and area efficiency of the link are 1 pj/b and 0.15 mm 2 /Gbps, respectively, which are the same as those of two-chip integration.