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An experimental 80-ns 1-Mbit DRAM with fast page operation

1985; Institute of Electrical and Electronics Engineers; Volume: 20; Issue: 5 Linguagem: Inglês

10.1109/jssc.1985.1052415

1558-173X

H.L. Kalter, Peter Coppens, W.F. Ellis, J.A. Fifield, D.J. Kokoszka, T.L. Leasure, Christopher P. Miller, Q. Nguyen, R.E. Papritz, Caitlyn Patton, J. Poplawski, S. W. Tomashot, W.B. van der Hoeven,

VLSI and Analog Circuit Testing

An experimental general purpose 5-V 1-Mb dynamic RAM has been designed for increased performance, high density, and enhanced reliability. The array consists of a one-device overlapped I/O cell with a metal bitline architecture. The cell measures 4.1 /spl mu/m by 8.8 /spl mu/m, which yields a chip size of 5.5 mm by 10.5 mm with an array to chip area ratio of 65.5%. The chip was designed in a double-poly single-metal NMOS technology with selected 1-/spl mu/m levels and an average feature size of 1.5 /spl mu/m. Key design features include a fast page mode cycle with minimum column precharge delay and improved protection for short error rate using a boosted word-line after sense amplifier set scheme. The CAS access time is 40 ns and the cycle is 65 ns at 4.5 V and 85/spl deg/C. The RAS access time is 80 ns and the cycle is 160 ns at 4.5 V and 85/spl deg/C with a typical active power of 625 mW. The chip is usable as a X1, X2, or X4 with the use of block select inputs and the selected package option. The package options include a 500-mil/SUP 2/ pin grid array module with 23 pins, and a 22 pin or 26 pin 300-mil surface solder plastic package.