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A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage

2009; Institute of Electrical and Electronics Engineers; Volume: 44; Issue: 1 Linguagem: Inglês

10.1109/jssc.2008.2006439

1558-173X

Ferdinando Bedeschi, Rich Fackenthal, Claudio Resta, Enzo Michele Donze, Meenatchi Jagasivamani, E. Buda, F. Pellizzer, David W. Chow, A. Cabrini, G Calvi, Roberto Faravelli, A. Fantini, G. Torelli, D. Mills, Roberto Gastaldi, G. Casagrande,

Semiconductor materials and devices

In this paper, a 90-nm 128-Mcell non-volatile memory based on phase-change ${\hbox{Ge}}_{2}\mathchar"707B {\hbox{Sb}}_{2}\mathchar"707B {\hbox{Te}}_{5}$ alloy is presented. Memory cells are bipolar selected, and are based on a $\mu{\hbox{trench}}$ architecture. Experimental investigation on multi-level cell (MLC) storage is addressed exploiting the chip MLC capability. To this end, a programming algorithm suitable for 2 bit/cell storage achieving tightly placed inner states (in terms of cell current or resistance) is proposed. Measurements showed the possibility of placing the required distinct cell current distributions, thus demonstrating the feasibility of the MLC phase-change memory (PCM) storage concept. Endurance tests were also carried out. Cumulative distributions after 2-bit/cell programming before cycling and after 100 k program cycles followed by 1 h/150 $\,^{\circ}{\hbox{C}}$ bake are presented. Experimental results on MLC endurance are also provided from a 180-nm 8-Mb PCM demonstrator with the same $\mu{\hbox{trench}}$ cell structure.