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Scheduling semiconductor device test operations on multihead testers

1999; IEEE Computer Society; Volume: 12; Issue: 4 Linguagem: Inglês

10.1109/66.806130

1558-2345

Tali Freed, Robert C. Leachman,

VLSI and FPGA Design Techniques

Past attempts to devise scheduling methods for the device test operations of semiconductor manufacturing firms fail to address a significant characteristic of multiple-head test systems-the dependency of processing rates on the lots processed simultaneously on the testers. Since the problem has never been modeled accurately in the scheduling literature, feasibility and performance of previously proposed scheduling methodologies for multihead testers may not be accurately assessed. In this paper, we describe the multihead tester scheduling problem, present an enumeration solution procedure, and illustrate the problems of previously suggested tester scheduling algorithms.