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A study of performance issues of the ATLAS event selection system based on an ATM switching network

1996; Institute of Electrical and Electronics Engineers; Volume: 43; Issue: 1 Linguagem: Inglês

10.1109/23.486011

1558-1578

D. Calvet, K. Djidi, P. Le Dû, I. Mandjavidze, M. Costa, T.-P. Dufey, M. Letheren, C Paillard,

Particle physics theoretical and experimental studies

Asynchronous Transfer Mode (ATM) is a candidate technology to implement the high performance network in the data collection system for the ATLAS experiment.This work presents the results of modelling and simulation studies which aim at integrating the detailed organization of the detector read-out, the trigger requirements and the capabilities of ATM switching networks.The status of hardware development of small scale demonstrators is outlined. I. INTRODUCTIONThe next generation of High Energy Physics experiments, ATLAS [1] and CMS [2], proposed at the CERN Large Hadron Collider (LHC), will place heavy demands on the data acquisition and on-line filtering systems.A variable portion of the 10 6 -10 8 detector channels in those experiments will be fired by tens of interactions created by two bunches of hadrons colliding at a 40 MHz rate.Sophisticated multi-level selection systems will reduce the raw data flow from a few tens of TBytes/s to the several tens of Mbyte/s that will then be recorded on tape for subsequent off-line analysis.A first reduction of this data will be carried out by fast pipe-lined logic that will retain only those events that satisfy some simple geometrical and energy deposition criteria.After this first level selection the remaining data bandwidth is expected to be of the order of ~1000 Gbit/s.Traditional busbased data acquisition (DAQ) systems are not adequate to handle this high bandwidth.Several data acquisition conceptual models have been proposed for use downstream of the first level trigger ([1], [2]).The RD-31 project [3] aims at evaluating a new, parallel approach to data acquisition based on the use of standard Asynchronous Transfer Mode (ATM) packet switching technology [4].This technology holds the promise of becoming a "universal" communication standard, unifying the telecommunications and local area network markets on the time scale of the LHC.A group of collaborators within RD-31 is involved in the ATLAS experiment.It focuses its efforts on the architecture design and simulation studies adapted to the ATLAS trigger system based on the ATM technology.In this paper we propose an integrated architecture for the level 2 and level 3 selection and data read-out systems.It is based on the so-called data "Pull" control strategy.We discuss the relative merits of this approach and evaluate its performance by means of simulations.This paper is organized as follows.Section II describes the principles of the ATLAS event selection and data read-out models.Some of the system bandwidth requirements are presented in section III.The motivations leading to the choice of ATM for our application are given in section IV.Our proposed "integrated Pull architecture" is described in section V.The system that we have modelled and the corresponding simulation results are presented in section VI.The status of two hardware demonstrators is out-lined in section VII.Future plans and a summary are presented in sections VIII and IX. II. EVENT SELECTION AND DATA READ-OUT IN ATLAS A. The Basic PrinciplesThe ATLAS trigger consists of three logical levels, shown schematically in Fig. 1.Beam crossing interactions occur at a rate of 40 MHz.At the nominal luminosity of 10 34 cm -2 s -1 , the input event rate resulting from the level 1 trigger threshold cuts is estimated to be approximately 30-40 kHz.A safe design value of 100 kHz has been adopted.The level 1 trigger is without deadtime, because all the data are pipelined during the fixed 2 µs latency needed to decide whether to accept or reject the event candidates.