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Dynamic capacity modeling in semiconductor assembly manufacturing

2006; Taylor & Francis; Volume: 46; Issue: 3 Linguagem: Inglês

10.1080/00207540600932020

1366-588X

M. Tao Zhang, Jiali Fu, Enshen Zhu,

Assembly Line Balancing Optimization

Abstract It is very challenging to gain a competitive advantage in semiconductor assembly manufacturing, mainly due to widely and quickly fluctuating customer requests, complicated workflows, and the co-existence of new and aging technology/equipment. In late 2003, Intel Shanghai experienced capacity degradation, mainly due to the introduction of multiple-chip products with re-entrant workflows. In response, we applied the joint protective capacity methodology to semiconductor assembly manufacturing and developed a dynamic capacity model that captures the variability of re-entrant manufacturing systems. Protective capacity and other parameters at constrained and near-constrained stations are regularly tracked and adjusted to accurately reflect line execution variability in terms of equipment, staff, and work-in-process. With the implementation and continuous improvement of these methodologies, we increased the factory output by 200% without major capital investment (avoiding millions of dollars in capital spending), cut unit cost by 30%, and brought down subcontractor costs by 26%, which resulted in cash savings of over ten million dollars for Intel. ¶Given the sensitive and proprietary nature of the semiconductor environment, only normalized performance data are used in this paper. Keywords: Re-entrant flowCapacity modelingTheory of constraints (TOC)Joint protective capacity (JPC)Semiconductor manufacturing Acknowledgements We thank the anonymous reviewers of this paper for their constructive feedback. This project was the recipient of two Intel PD Recognition Awards and the Intel Assembly and Test Manufacturing Achievement Award. The preliminary versions of this paper were published in the Intel Assembly & Test Technology Journal (2004) and the IEEE International Conference on Automation Science and Engineering (2005). We would like to thank CB Soon (Intel PD General Manager) for his coaching. We also thank Bian Cheng Gang and Stella Zhu (Intel PD1 Factory Managers), Steven Jiao (Intel PD1 Engineering Manager), and the PD1 Assembly Output Max team for their contributions and assistance in implementing the capacity model. Special thanks to Kenneth Daly from Intel Ireland for introducing the application of JPC. Thanks also go to Sean Sweat from Massachusetts Institute of Technology and Kimberly Bryant from Intel Corporation for their helpful comments. Notes ¶Given the sensitive and proprietary nature of the semiconductor environment, only normalized performance data are used in this paper.