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An improved technique for circuit board interconnect test

1992; Institute of Electrical and Electronics Engineers; Volume: 41; Issue: 5 Linguagem: Inglês

10.1109/19.177344

1557-9662

J.C. Chan,

3D IC and TSV technologies

The author reviews the self-test features of the IBM RISC System/6000 processor circuit board. Based on this, a technique is described to automate the interconnect wiring test, which is performed as part of the power-on self-test (POST) at the manufacturing stage. Essential to the implementation is the idea of response compression using the multiple input signature registers (MISR). Interconnect wiring defects are diagnosed by comparing the content of the MISR with the expected result after a simple test procedure. Formal analysis shows that a high test coverage can be achieved for the most commonly occurring defects. As a result, the proposed technique has the advantages of low overhead cost and easy fault detection. >