Process and performance comparison of an 8K × 8-bit SRAM in three stacked CMOS technologies
1985; Institute of Electrical and Electronics Engineers; Volume: 6; Issue: 10 Linguagem: Inglês
10.1109/edl.1985.26225
ISSN1558-0563
AutoresL.R. Hite, R. Sundaresan, S.D.S. Malhi, Hon Wai Lam, A.H. Shah, R.K. Hester, P.K. Chatterjee,
Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoUsing self-aligned and non-self-aligned stacked CMOS technologies experimental 8K × 8-bit static random-access memories (SRAM'S) have been fabricated. Hydrogen passivation has been used to improve the performance of polysilicon devices. An 8K × 8-bit SRAM using non-self-aligned memory cells and employing a CW argon laser to anneal the second (active) polysilicon layer has also been fabricated. The fabrication methods and performances of all three SRAM's have been compared.
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