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Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels

2011; Institute of Electrical and Electronics Engineers; Volume: 32; Issue: 4 Linguagem: Inglês

10.1109/led.2011.2107498

1558-0563

Chun-Jung Su, Tzu‐I Tsai, Yu-Ling Liou, Zer-Ming Lin, Horng‐Chih Lin, Tien‐Sheng Chao,

Semiconductor materials and devices

In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.