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Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard thin shrink small outline packages

2001; Institute of Electrical and Electronics Engineers; Volume: 24; Issue: 2 Linguagem: Inglês

10.1109/6040.982843

1557-9980

Tzyy‐Sheng Horng, Sung-Mao Wu, Chi-Tsung Chiu, Chih-Pin Hung,

Electronic Packaging and Soldering Technologies

The electrical models of bump chip carrier (BCC) packages have been established based on the S-parameter measurement. When compared to the standard thin shrink small outline packages (TSSOPs), BCC packages show much smaller parasitics in the equivalent model. In the simulation, the insertion and return losses for a packaged 50-/spl Omega/ microstrip line are calculated against frequency. BCC packages are also less lossy than TSSOPs over a wide frequency range. By setting a random variable with Gaussian distribution varied within a certain range for each equivalent circuit element of the packages, the Monte Carlo analysis has been performed to study the package effects on a GaAs heterojunction bipolar transistor (HBT). Again, BCC packages cause less decrement of HBT unity-gain bandwidth than TSSOPs.