A Novel Strain Method for Enhancement of 90-nm Node and Beyond FUSI-Gated CMOS Performance
2007; Institute of Electrical and Electronics Engineers; Volume: 28; Issue: 2 Linguagem: Inglês
10.1109/led.2006.889633
ISSN1558-0563
AutoresChien-Ting Lin, Yean-Kuen Fang, Wen‐Kuan Yeh, Tung-Hsing Lee, Ming-Syan Chen⋆, Chieh-Ming Lai, Che-Hua Hsu, Liangwei Chen, Liwei Cheng, Mike Ma,
Tópico(s)Semiconductor materials and devices
ResumoA novel strain engineering technique for a fully silicided (FUSI) metal gate called contact etch stop layer (CESL)-enveloped FUSI was developed for the first time. A CESL was deposited prior to the FUSI RTP2 (the second rapid thermal process of FUSI gate formation) to confine the Ni x Si FUSI. Then, the phase transfer and volume change of the enveloped FUSI after RTP2 induced a tensile stress to enhance I ON . For example, 500 degC RTP2 induced 1-GPa tensile stress on a blanket wafer test and gained 10% improvement in the I ON of the n-channel metal-oxide-semiconductor. The mechanisms of the improvement were also nicely supported by transmission-electron-microscope cross-section analysis, X-ray-diffraction spectrum, and simulation confirmation data
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