1024 bit bubble memory chip
1973; IEEE Magnetics Society; Volume: 9; Issue: 3 Linguagem: Inglês
10.1109/tmag.1973.1067585
ISSN1941-0069
AutoresL. Bosch, R. G. Downing, G. E. Keefe, Laurence Rosier, K. D. Terlep,
Tópico(s)Power Systems and Renewable Energy
ResumoA 1024-bit bubble memory chip having a storage density of 1.5 × 10 6 bits/in 2 has been designed, fabricated, and tested. The chip organization consists of two identical, independent, 512-bit major-minor-loop configurations. All device functions have been operated at the chip level at 500 kHz. The bubble chip has been mounted in a ceramic module assembly containing a sense amplifier chip, the in-plane field coils, and the permanent-magnet bias field. All device functions have been operated at the module level at 100 kHz, and the nonvolatility capability has been established.
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