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Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

2007; Institute of Electrical and Electronics Engineers; Volume: 42; Issue: 1 Linguagem: Inglês

10.1109/jssc.2006.885057

1558-173X

Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kei Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, T. Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie,

VLSI and Analog Circuit Testing

Hierarchical power distribution with a power tree has been developed. The key features are a power-tree structure with three power-tree management rules and a distributed common power domain implementation. The hierarchical power distribution supports a fine-grained power gating with dozens of power domains, which is analogous to a fine-grained clock gating. Leakage currents of a 1 000 000-gate power domain were effectively reduced to 1/4000 in multi-CPU SoCs with minimal area overhead