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400-MHz random column operating SDRAM techniques with self-skew compensation

1998; Institute of Electrical and Electronics Engineers; Volume: 33; Issue: 5 Linguagem: Inglês

10.1109/4.668992

1558-173X

T. Hamamoto, M. Tsukude, Kazutami Arimoto, Y. Konishi, T. Miyamoto, H. Ozaki, Masahiro Yamada,

Parallel Computing and Optimization Techniques

High-speed data transfer is a key factor in future main memory systems. DDR SDRAM (double-data-rate synchronous-DRAM) is one of the candidates for high-speed memory. In this paper we present three techniques to achieve a short access time and high data transfer rate for DDR-SDRAM's. First, a self-skew compensating technique enables 400-Mbit/s address and data detection. Second, a novel trihierarchical WL scheme realizes multibank operation without access or area penalties. Third, an interleaved array access path doubles the array operating frequency and it enables 400-MHz random column operation. A 16-bank 256-Mbit DDR SDRAM circuit has been designed, and the possibility of the realization of random column 200 MHz/spl times/32 DDR operation, namely, 1.6-Gbyte/s data rate operation, has been confirmed.