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Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

2009; Institute of Electrical and Electronics Engineers; Volume: 56; Issue: 8 Linguagem: Inglês

10.1109/tcsii.2009.2025627

1558-3791

Young‐Won Kim, Jooseong Kim, Jae-Hyuk Oh, Yoon-Suk Park, Jong-Woo Kim, Kwang‐Il Park, Bai‐Sun Kong, Young-Hyun Jun,

Advancements in PLL and VCO Technologies

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-mum CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.