Portal de Periódicos da CAPES

Precise CMOS current sample/hold circuits using differential clock feedthrough attenuation techniques

1995; Institute of Electrical and Electronics Engineers; Volume: 30; Issue: 1 Linguagem: Inglês

10.1109/4.350189

1558-173X

Chung‐Yu Wu, Chih‐Cheng Chen, Jyh-Jer Cho,

Integrated Circuits and Semiconductor Failure Analysis

New CMOS current sample/hold (CSH) circuits capable of overcoming the accuracy limitations in conventional circuits without significantly reducing operating speed are proposed and analyzed. A novel differential clock feedthrough attenuation (DCFA) technique is developed to attenuate the signal-dependent clock feedthrough errors. Unlike conventional techniques, the DCFA circuit allows the use of dynamic mirror techniques, and results in no additional finite output resistance errors or device mismatch errors. The test chip of the proposed fully differential CSH circuit with multiple outputs has been fabricated in 1.2-/spl mu/m CMOS technology. Using a single 5-V power supply, experimental results show that the signal-dependent clock feedthrough error current is less than /spl plusmn/0.4 /spl mu/A for the input currents from -550 /spl mu/A to 550 /spl mu/A. The acquisition time for a 900-/spl mu/A step transition to 0.1% settling accuracy is 150 ns. For a 410-/spl mu/A/sub p-p/ input at 250 MHz with the fabricated fully-differential CSH circuit clocked at 4 MHz, a total harmonic distortion of -60 dB, and a signal-to-noise ratio of 79 dB have been obtained. The active chip area and power consumption of the fabricated CSH circuit are 0.64 mm/sup 2/ and 20 mW, respectively. Both simulation and experimental results have successfully verified the functions and performance of the proposed CSH circuits. >