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A practical methodology for verifying pipelined microarchitectures

2003; Institute of Electrical and Electronics Engineers; Volume: 20; Issue: 4 Linguagem: Inglês

10.1109/mdt.2003.1214347

1558-1918

Ravi Hosabettu, G. Gopalakrishnan, Mandayam Srivas,

Parallel Computing and Optimization Techniques

Complete formal verification has thus far never been achieved for a state-of-the-art, high-performance commercial microprocessor. However, this article presents a completion functions methodology, based on theorem proving, that has been applied successfully to a large variety of example pipelined architectures.