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Performance Models of Binary Synchronous Communications Multipoint Circuits Over Virtual Private-Line Frame Relay Networks

1988; Institute of Electrical and Electronics Engineers; Volume: 67; Issue: 5 Linguagem: Inglês

10.1002/j.1538-7305.1988.tb00253.x

2376-676X

Robert Cole,

Interconnection Networks and Systems

This paper discusses performance models of 3270 binary synchronous communications (BSC) multipoint circuits over virtual private-line frame-relay networks. The models are used to identify the key network functionality needed to minimize end-to-end delays perceived by users. We derive new models that determine the mean total transaction time between the end systems (a front-end processor and cluster controllers on multipoint circuits). The models capture queueing delays — an important component of transaction time. The models also incorporate important BSC protocol parameters, including system parameters of the front-end processor. A performance analysis based on the models demonstrates the sensitivity of the BSC protocol to the functionality at the network edge. For a simple virtual private-line replacement, egress pipelining is a necessity to maintain acceptably low end-to-end delays. For more complex replacements, where access line speeds can be economically increased and front-end-processor system generation parameters changed, the analysis demonstrates the value of edge polling.