Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
2008; Institute of Electrical and Electronics Engineers; Volume: 29; Issue: 7 Linguagem: Inglês
10.1109/led.2008.2000617
ISSN1558-0563
AutoresBing Yang, Kavitha D. Buddharaju, Selin Hwee-Gee Teo, Navab Singh, G. Q. Lo, Dim‐Lee Kwong,
Tópico(s)Advancements in Semiconductor Devices and Circuit Design
ResumoThis letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires with diameter ~20 nm are achieved from lithography and dry-etch defined Si-pillars with subsequent oxidation. The surrounding gate length is controlled using etch back of the sacrificial oxide. N-MOS devices thus fabricated with gate length ~150 nm showed excellent transistor characteristics with large drive current (1.0 times 10 3 muA/mum), high I on /I off ratio (~10 7 ), good subthreshold slope (~80 mV/dec) and low drain-induced barrier lowering (~10 mV/V). Along with good electrical characteristics, the use of low cost bulk wafers, and simple gate definition process steps could make this device a suitable candidate for next generation technology nodes.
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