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"Depletion isolation effect" of surrounding gate transistors

1997; Institute of Electrical and Electronics Engineers; Volume: 44; Issue: 12 Linguagem: Inglês

10.1109/16.644659

1557-9646

Mamoru Terauchi, N. Shigyo, A. Nitayama, F. Horiguchi,

Integrated Circuits and Semiconductor Failure Analysis

Sub-half-micron surrounding gate transistors (SGTs) were fabricated and their current-voltage (I-V) characteristics were investigated. Even in a SGT whose Si pillar is not fully depleted (e.g., 0.6 /spl mu/m SGT), by using the lower diffusion layer of the Si pillar as drain and applying sufficiently high voltage, I-V characteristics inherent to fully depleted devices (i.e. subthreshold swing as low as 60 mV/dec., lowered threshold voltage independent of substrate bias voltage) were observed ("depletion isolation effect").