Portal de Periódicos da CAPES

A 4-ns 4K*1-bit two-port BiCMOS SRAM

1988; Institute of Electrical and Electronics Engineers; Volume: 23; Issue: 5 Linguagem: Inglês

10.1109/4.5921

1558-173X

T.-S. Yang, Mark Horowitz, B.A. Wooley,

Semiconductor materials and devices

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K*1-bit two-port memory integrated in a 1.5- mu m 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100 degrees C. >