A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM
1989; Institute of Electrical and Electronics Engineers; Volume: 24; Issue: 5 Linguagem: Inglês
10.1109/jssc.1989.572586
ISSN1558-173X
AutoresMakoto Suzuki, S. Tachibana, Atsuo Watanabe, S. Shukuri, Hiroyoshi Higuchi, T. Nagano, K. Shimohigashi,
Tópico(s)Parallel Computing and Optimization Techniques
ResumoA 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct column sensing scheme having a cascode differential amplifier. As a result of extensive use of high-speed bipolar ECL circuits with self-aligned bipolar transistors, the RAM attains high-speed performance without degrading the low-power BiCMOS RAM characteristics. >
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