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A Dynamically Reconfigurable Pixel Processor System Based on Power/Energy-Performance-Accuracy Optimization

2012; Institute of Electrical and Electronics Engineers; Volume: 23; Issue: 3 Linguagem: Inglês

10.1109/tcsvt.2012.2210664

1558-2205

Daniel Llamocca, Marios S. Pattichis,

Advanced Memory and Neural Computing

We introduce a dynamically reconfigurable framework for implementing single-pixel operations. The system relies on a multiobjective optimization scheme that generates Pareto-optimal realizations in the power/energy-performance-accuracy (PPA/EPA) spaces. The Pareto-optimal realizations and their PPA/EPA values are stored in DDR-SDRAM and can be chosen dynamically to meet time-varying constraints. Results are shown in terms of power, accuracy (peak signal-to-noise ratio) of the resulting image, and performance in frames per second. Dynamic PPA/EPA management is implemented using dynamic partial reconfiguration and dynamic frequency control.