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Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM

1990; Institute of Electrical and Electronics Engineers; Volume: 25; Issue: 2 Linguagem: Inglês

10.1109/4.52180

1558-173X

Hiroshi Miyamoto, T. Yamagata, S. Mori, T. Aono, I. Ogoh, M. Yamada,

Semiconductor materials and devices

Improved circuits for a 4-Mb CMOS DRAM are described. In one of them, called the effective one-shot gate address buffer, the input address is provided to the gate of a transistor, and a gating transistor located between the input node of the buffer and the transistor is controlled by an equivalent one-shot pulse with sufficient high level. This reduces the row address hold time and also RAS-bar access time. A standby current limitation circuit eliminates the standby current at the input stage of the buffer even with TTL-level input voltage. Test-mode hidden refresh is achieved without test-mode resetting, which enhances the testability and relaxes the test sequence. The RAM employs a 0.8- mu m twin-well CMOS process technology and a stacked capacitor with a storage capacitance of 35 fF. A 58-ns RAS-bar access time and a 65-mA active current at 160-ns cycle are achieved in a die size of a 6.84 mm*14.95 mm. The RAM is housed in a 350-mil small-outline J-leaded package and a 400-mil zig-zag in-line package. >