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A 3.3-V 800-nV/sub rms/ noise, gain-programmable CMOS microphone preamplifier design using yield modeling technique

1993; Institute of Electrical and Electronics Engineers; Volume: 28; Issue: 8 Linguagem: Inglês

10.1109/4.231328

1558-173X

Germano Nicollini, Carlo Guardiani,

Advancements in PLL and VCO Technologies

A 3.3-V CMOS low-noise gain-programmable microphone amplifier with a high-impedance balanced input is presented. The preamplifier allows gains from 20 to 35 dB to be set by software control in 1-dB steps with 0.05-dB accuracy. Typical measured V/sub OS/ is 0.8 mV, V/sub OS/ drift is 1 mu V/C, input-referred p-weighted noise is 0.8 mu V/sub rms/ and total harmonic distortion (THD) is -70 dB. The active area is about 350 mils/sup 2/, and power consumption is 1.7 mW at 3.3-V supply and 2.9 mW at 5-V supply. These results have been obtained through an intensive use of the yield modeling technique for yield-performance optimization during the design phase, and by applying a common-centroid cross-coupled strategy to the layout of all the ideally matched MOS transistors in the input stage. >