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Analogue circuit design methodology using self‐cascode structures

2013; Institution of Engineering and Technology; Volume: 49; Issue: 9 Linguagem: Inglês

10.1049/el.2013.0554

1350-911X

Ki–Ju Baek, Jie-Wei Gim, H.‐S. Kim, K.‐Y. Na, Nam Soo Kim, Young-Hoon Kim,

Advanced MEMS and NEMS Technologies

Electronics LettersVolume 49, Issue 9 p. 591-592 Circuits and systemsFree Access Analogue circuit design methodology using self-cascode structures K.-J. Baek, K.-J. Baek Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorJ.-M. Gim, J.-M. Gim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorH.-S. Kim, H.-S. Kim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorK.-Y. Na, K.-Y. Na Department of Semiconductor Electronics, Chungbuk Provincial College, Okcheon, Chungbuk, Republic of KoreaSearch for more papers by this authorN.-S. Kim, N.-S. Kim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorY.-S. Kim, Corresponding Author Y.-S. Kim [email protected] Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this author K.-J. Baek, K.-J. Baek Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorJ.-M. Gim, J.-M. Gim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorH.-S. Kim, H.-S. Kim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorK.-Y. Na, K.-Y. Na Department of Semiconductor Electronics, Chungbuk Provincial College, Okcheon, Chungbuk, Republic of KoreaSearch for more papers by this authorN.-S. Kim, N.-S. Kim Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this authorY.-S. Kim, Corresponding Author Y.-S. Kim [email protected] Department of Semiconductor Engineering, Chungbuk National University, Cheongju, Chungbuk, 361-763 Republic of KoreaSearch for more papers by this author First published: 01 April 2013 https://doi.org/10.1049/el.2013.0554Citations: 28AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Abstract A new analogue circuit design methodology using independently optimised self-cascode (SC) structures is proposed. Based on the concept of the dual-workfunction-gate structures, which are equivalent to SC structures, transconductance and output resistance optimised SC MOSFETs were used in the differential input and output stages, respectively. An operational amplifier (opamp) with the proposed design methodology using standard 0.18 µm CMOS technology was designed to provide better performance. The measured DC gain of the fabricated opamp with independently-optimised SC MOSFETs was approximately 12 dB higher than that of the conventional opamp. Introduction The device dimensions of modern CMOS technologies have been scaled down to the nanometre regime, and the power supply is also reduced to an ultra-low voltage down to 0.5V. Enhancing the analogue circuit performance using the general analogue circuit design methodology, such as the use of long channel devices and conventional cascode structures, is difficult because of the channel length modulation (CLM) effect, threshold voltages (VTH) and output swing limitations. The self-cascode (SC) is used widely to reduce the CLM effect and is used in the design of a low voltage operational transconductance amplifier (OTA), which shows a high DC gain and output voltage swing [1]. On the other hand, the large channel width and length (W/L) ratio of two MOSFETs in the SC structure is one of its disadvantages. Asymmetric VTH SC structures using low VTH MOSFETs have been proposed [2]. This approach requires a lower W/L ratio, but additional fabrication processing steps are unavoidable. The SC structure can also be used for an indirect compensation technique for the high-speed operational amplifier (opamp) [3]. The dual-workfunction-gate (DWFG) MOSFET is a newly introduced transistor with an asymmetrically-doped poly-silicon gate to increase the output resistance (rout) and transconductance (gm) [4]. The length of the source side gate with a higher workfunction is a major factor for optimising rout and gm. Surprisingly, the DWFG MOSFET is a similar concept to the SC structure and can be applied to analogue circuit design but this technique requires complicated process steps. This Letter proposes a new analogue circuit design methodology using the SC structure and concept reported elsewhere [4]. The proposed method used standard CMOS technologies and the channel lengths of the SC structure were optimised separately for high gm and rout. Using the optimised SC MOSFETs, a two-stage opamp with higher gain was fabricated and measured to verify the proposed idea. Proposed circuit and methodology Fig. 1 shows the simulated gm and gout (= 1/rout) of the SC MOSFET against channel length. The p-channel MOSFETs (pMOSFETs) of MS and MD are connected in series and a forward body bias for MD is applied to reduce VTH without using low VTH MOSFETs to avoid additional fabrication processing steps. TSMC 0.18 µm CMOS technology was used to both simulate and fabricate the proposed SC MOSFET. Fig 1Open in figure viewerPowerPoint Simulated gm and gout of SC pMOSFET against channel length The condition of |VTH,MS| − |VTH,MD| ≥ |VDS.sat,MD| was satisfied by forward-biasing the body of MD to give a high rout and output voltage swing [2]. With VCM = 1.4, VTH was reduced by approximately 0.1 V. The total channel length (L) is 1.0 µm (LMS + LMD = 1.0 µm) and an identical channel width of 24 µm is used for MD and MS. The SC MOSFET with LMS = 0.8 µm showed the lowest gout characteristics compared to the single pMOSFET (L = 1.0 µm) and the SC MOSFET with LMS = 0.5 µm. Previously, the main purpose of the SC structure was to reduce the CLM effect [2]. Fig. 1, however, shows that in addition to the lower gout characteristics, enhanced gm characteristics were also observed in the SC MOSFET [4], which can be used to enhance the performance of the analogue circuit. In contrast to the gout characteristics, the SC MOSFET with LMS = 0.2 µm showed the highest gm. The transistor MS of the SC structure is in the triode regime and the resistance depends on the gate bias. The effective gm of the SC structure is close to the gm of transistor MS. Fig. 1 shows that the channel length of the transistor MS is a critical parameter for the gm and gout optimisation of SC structures. Fig. 2a shows the measured gm characteristics of the SC MOSFET with LMS = 0.2 µm optimised for gm, and Fig. 2b shows the measured gout characteristics of the SC MOSFET with LMS = 0.8 µm optimised for gout. The measured gm and gout of the optimised SC MOSFETs at VSD = 0.9 V and VSG = 0.6 V were 0.23 mS and 0.20 µS, respectively, which is approximately three times improvement compared to those of the single pMOSFET. Fig 2Open in figure viewerPowerPoint Measured gm (Fig. 2a) and gout (Fig. 2b) characteristics of optimised SC MOSFETs Fig. 3a shows a two-stage opamp using the proposed SC MOSFETs. To enhance the performance of the opamp, the optimised gm SC MOSFETs (LMS = 0.2 µm) were used for the differential input pairs, MP1-MP4, and the optimised rout SC MOSFETs (LMS = 0.8 µm) were used in the current mirror, MP5-MP10. The supply voltage (VDD) and forward body bias voltage (VCM) were 1.8 V and 1.4 V, respectively. The tail current of the differential stage was 20 µA. Fig. 3b shows the simulated frequency response of both the conventional opamp with single pMOSFETs and the opamp with the proposed SC pMOSFETs. The DC gain of the opamp with the proposed SC pMOSFETs was 94 dB, which is 10 dB higher than that of the conventional opamp. The gain bandwidth was 12 MHz. Fig 3Open in figure viewerPowerPoint Circuit diagram of two-stage opamp using proposed optimised SC MOSFETs (Fig. 3a) and simulated frequency response of opamps (Fig. 3b) The conventional opamp with the single pMOSFETs and the opamp with the proposed SC pMOSFETs were fabricated using TSMC 0.18 μm CMOS technology and the measurement results are summarised in Table 1. The measured DC gains of the opamp using the proposed SC and the conventional opamp were 78.4 and 66.0 dB, respectively. The enhanced gm and rout of the proposed SC structure resulted in a higher DC gain of the opamp. The optimised SC technique is applied only to the pMOSFETs due to body biasing problems. If triple well technology or SOI CMOS technology is available, nMOSFETs with the optimised SC structures can be used, which will enhance the DC gain further. Table 1. Measured performance comparison of opamps Items Conv. opamp opamp with SC Supply voltage 1.8 V 1.8 V Tall current 20 µA 20 µA DC gain 66.0 dB 78.4 dB CMRR 66.4 dB 65.4 dB Slew rate (rising), CL = 15 pF 0.46 V/μs 0.56 V/μs Output swing 56.8 mV − 1.7 V 57.7 mV − 1.7 V Conclusion A new analogue circuit design approach using SC structures and the concept of the dual-workfunction-gate structures has been described. Optimising the channel length of the source side MOSFET of the SC structure, highest transconductance and output resistance MOSFETs were obtained and utilised in the input differential stages and output stages of the opamp, respectively, to obtain better performance. A two-stage opamp using the proposed SC MOSFETs was designed. The measured DC gain of the fabricated opamp using the proposed SC MOSFETs was approximately 12 dB higher than that of the conventional opamp. The proposed SC MOSFETs and design methodology is one of promising solutions for low voltage analogue circuit design particularly in nanometre regime CMOS technology. Acknowledgment This research was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) no. 2011-0006764. References 1Gerosa, A., Neviani, A.: 'Enhancing output voltage swing in low-voltage micro-power OTA using self-cascode', Electron. Lett., 2003, 39, (8), pp. 638– 639 (https://doi/org/10.1049/el:20030436) 2Fujimori, I., Sugimoto, T.: 'A 1.5 V, 4.1mW dual-channel audio delta-sigma D/A converter', IEEE J. Solid-State Circuits, 1998, 33, (12), pp. 1863– 1870 (https://doi/org/10.1109/4.735525) 3Baker, R.J.: ' CMOS: circuit design, layout, and simulation' (Wiley-IEEE Press, NJ, 2007) 4Na, K.-Y., Baek, K.-J., Kim, Y.-S.: 'N-channel dual-workfunction-gate MOSFET for analog circuit applications', IEEE Trans. Electron Devices, 2012, 59, (12), pp. 3273– 3279 (https://doi/org/10.1109/TED.2012.2219865) Citing Literature Volume49, Issue9April 2013Pages 591-592 FiguresReferencesRelatedInformation